Electronic circuit-ah chuan crystal oscillator hi clock source hman tlanglawn ber pakhat a ni. Crystal oscillator startup dik leh stable operation neih theih nan circuit chhunga external load capacitor te chu a load capacitance (CL) angin uluk taka design a ngai a ni. Capacitor matching dik lo chuan oscillation-ah harsatna a thlen thei a, frequency deviation a tipung thei a, system instability pawh a thlen thei bawk.
He thuziak hian crystal oscillator load capacitance awmzia te, pawn lam capacitor te chhiar dan te, circuit design-a thil tangkai tak tak ngaihtuah dan te chipchiar takin a tarlang dawn a ni.
Ⅰ. Crystal oscillator load capacitance (CL) chu engzat nge ni?
Crystal siamtute chuan datasheet-ah hian nominal load capacitance value (CL) an tarlang tlangpui a, chu chu 18pF, 20pF, 12pF, etc. Hei hian crystal chu a nominal oscillation frequency a thlen theih nan capacitive load hnuaia calibrate a nihna a entir a ni.
Phên dangin sawi ila, crystal oscillator hian frequency dik tak a output thei a, chu chu equivalent load capacitance chu CL a nih chauhvin a ni.
Ⅱ. Engtin Nge External Load Capacitor te hian Load Capacitance a nghawng?
Crystal oscillator circuit pangngai chuan a hnuaia mi ang hian a awm a:
C1 leh C2 hi pawn lam capacitor pahnih ground nena inzawm (a tlangpuiin SMD capacitor) an ni a;
XTAL terminal pahnih hi crystal oscillator pin pahnih nen an inzawm a;
Practice-ah chuan crystal-a equivalent load capacitance CL chu C1 leh C2-in series-in an chhut a, PCB leh package-in parasitic capacitance Cp an rawn luhtir nen an inzawm khawm a ni.
Ⅲ. Calculation Formula: CL atanga External Capacitor Value hi engtin nge kan hriat theih ang?
Equivalent load capacitance (CL) atana formula chu hetiang hi a ni:
Khawnge:
C1, C2: Pawn lam capacitor ground nena inzawm;
Cp: PCB traces, packaging, etc. hmanga rawn luh parasitic capacitance (a tlangpuiin 2pF atanga 5pF, simulation emaw experience emaw hmanga chhut theih)
CL: Crystal oscillator datasheet-a nominal load capacitance tarlan a ni.
【Entirna Entirna】
Crystal specification chu CL=18pF ni ta se, PCB parasitic capacitance Cp ≈ 5pF ni ta se. C1 leh C2 tana value dik tak chhut tur chuan:
A hmasa berin, value te chu formula ah hian substitute rawh:
C1=C2=C ni ta ila, formula hian hetiang hian a ti awlsam ang:
Chumi rah chhuah chu:
✅ Chuvangin, pawn lam capacitor hman tur rawtna chu: C1=C2=hi a ni.27pF a ni (Standard Value) a ni.
Ⅳ. Engvangin Nge Mismatched External Capacitors Hian Harsatna A Lo chhuah?
Frequency deviation: Pawn lam capacitor te hi a te lutuk emaw, a lian lutuk emaw a nih chuan crystal chu a nominal frequency atang chuan a deviate ang a, system clock error a awm ang.
Start-up harsatna emaw instability: Load tam lutuk hian gain a tihtlem a, hei hian crystal chu a start thei lo emaw, frequency jitter a tawk thei emaw a ni.
Power consumption tihpun: Load dik lo chuan crystal oscillator circuit-ah energy consumption sang zawk a thlen thin.
EMI tihpun: Oscillations nghet lo chuan spurious frequency a siam thei a, hei hian system electromagnetic compatibility (EMC) a nghawng thei a ni.
5. A ni. Design chungchanga rawtna leh Engineering kalphung
Crystal oscillator datasheet chu uluk takin enfiah rawh
CL value chu ruat rawh.
Circuit topology rawtna chu hrethiam rawh.
External capacitor value hrang hrang a tha em tih enfiah rawh.
2. Board environment tak tak kha han ngaihtuah teh
PCB simulation emaw experience emaw hmangin Cp estimate rawh.
High-speed emaw precision clock (eg, communication system, MCU main frequency > 100MHz) tan chuan, precise calculation emaw testing emaw neih a tha.
3. Symmetrical capacitor hmang rawh
A tlangpuiin C1=C2 chu frequency leh balance noise center turin a tha ber.
Asymmetrical design hi matching mamawh bik atan pawh hman theih a ni.
4. Debugging atan SMD capacitor array hmang ang che
SMD capacitor (eg, 10pF, 15pF, 22pF, 27pF, etc.) hmangin enchhin la, a fit dik tak chu hmu rawh;
Spectrum analyzer emaw oscilloscope emaw hmangin output stability leh frequency dik leh dik loh enfiah rawh.
6,UarFAQ
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Zawhna awm thei |
Chhannate chu |
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CL=12pF a nih chuan pawn lam capacitor te hi eng value nge ni tur? |
Cp=5pF a nih chuan C1=C2≈14pF a ni |
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Engvangin nge MCU thenkhatah chuan external capacitor an mamawh loh? |
Crystal oscillator circuit thenkhatah chuan load capacitor (eg, STM32) ah an insiam- a, chuvangin pawn lam capacitor a ngai lo. |
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Pawn lam capacitor inmil lo tak takte hian crystal oscillator hi a tichhia thei em? |
A tlangpuiin an hal lo ang a, an tichhia lovang a, mahse startup failure emaw frequency error emaw an thlen thei. |
Tawpna
Crystal oscillator atana external load capacitor design hi thil te tak te mahse a pawimawh hle a, clock system stability leh accuracy a nghawng nghal vek a ni. CL leh C1/C2 inkara calculation inzawmna hriatthiam a, PCB parasitic capacitance tak tak atanga parameter siamrem te hi oscillation rintlak leh frequency dik tak neih theihna tura pawimawh tak a ni.
High-speed digital system, inbiakpawhna hmanrua, emaw, clock mamawhna nasa tak nei system-ah chuan crystal oscillator load capacitance dik taka thlan leh inmil chu engineering hna pawimawh tak a ni a, ngaih pawimawh a ngai a ni.
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